Application Engineer

• Experience in Full custom Layout design with Virtuoso Schematic and
Layout-XL, Physical Verification (DRC, LVS, Parasitic Extraction, DFM), SKILL
• Advantages: Experience with automatic routing and placement of custom and
analog design, running simulation in Virtuoso-ADE, IC Packa

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Design Engineer for VLSI team

The job will include :
• Handling RTL design for new blocks and legacy blocks,
• Supporting chip integration
• Involvement in Block level synth, CDC, lint, integrating and supporting
DFT structures.
• Support BE team and Verification team during chip implementation for
design related topics as

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