חומרה
Minimum Requirements:
Bachelor's degree in Electrical Engineering.
6-10 years of VLSI front-end engineering experience.
Preferred Requirements:
Experience in SOC design and integration
Experience with Verilog design coding.
Bachelor's degree in Electrical Engineering.
6-10 years of VLSI front-end engineering experience.
Preferred Requirements:
Experience in SOC design and integration
Experience with Verilog design coding.
לפרטים נוספים
חומרה
AVIP engineer is responsible for development, support and maintenance of
verification IP for common communication or bus protocol, used for emulation
and simulation.
verification IP for common communication or bus protocol, used for emulation
and simulation.
לפרטים נוספים
חומרה
Responsibilities:
Mastering complex designs and applications in the field of deep learning in
close collaboration with HW team.
Mastering complex designs and applications in the field of deep learning in
close collaboration with HW team.
לפרטים נוספים
חומרה
Be part of a dynamic and motivated verification team, taking part in
developing from scratch a state of the art Satellite SoC through the
full life cycle: from design to production.
developing from scratch a state of the art Satellite SoC through the
full life cycle: from design to production.
לפרטים נוספים
חומרה
The Senior FPGA Verification Engineer will be responsible for high reliably
real-time FPGA verification activities.
Responsibilities Include:
High reliably FPGA logic design verification
High performance pipeline architectures verification
Verification of soft cores IP integration
Run unit verific
real-time FPGA verification activities.
Responsibilities Include:
High reliably FPGA logic design verification
High performance pipeline architectures verification
Verification of soft cores IP integration
Run unit verific
לפרטים נוספים
חומרה
Responsibilities:
Define and track detailed test plans for the different modules and top
levels.
Implement scalable test benches including checkers, reference models,
coverage groups in System Verilog.
Keep track of coverage metrics and bugs encountered and fixed.
Implement self-testing direct
Define and track detailed test plans for the different modules and top
levels.
Implement scalable test benches including checkers, reference models,
coverage groups in System Verilog.
Keep track of coverage metrics and bugs encountered and fixed.
Implement self-testing direct
לפרטים נוספים
חומרה
We are looking for highly motivated, and passionate, Verification engineer
to join our FPGA Team , for our next generation base-station products.
What you'll do:
Take part in FPGA Verification/Simulation activities.
Build & maintain new environments for several FPGAs using UVM methodology.
Br
to join our FPGA Team , for our next generation base-station products.
What you'll do:
Take part in FPGA Verification/Simulation activities.
Build & maintain new environments for several FPGAs using UVM methodology.
Br
לפרטים נוספים
חומרה
תחומי אחריות:
קבוצת FPGA/ASIC אחראית לספק את הדור הבא של
התקני ממשקי רשת, לספק רמת מורכבות חדשה כמו
גם לפיתוח מוצרים מהמתקדמים עבור הלקוחות
שלנו.
הזדמנות להשתתף בפיתוח קו מוצרי הדור הבא
שלנו, להכיר כמה מהטכנולוגיות המובילות
בתחום התקשורת (Network processors).
השתתפות בכל שלבי הפיתוח, הח
קבוצת FPGA/ASIC אחראית לספק את הדור הבא של
התקני ממשקי רשת, לספק רמת מורכבות חדשה כמו
גם לפיתוח מוצרים מהמתקדמים עבור הלקוחות
שלנו.
הזדמנות להשתתף בפיתוח קו מוצרי הדור הבא
שלנו, להכיר כמה מהטכנולוגיות המובילות
בתחום התקשורת (Network processors).
השתתפות בכל שלבי הפיתוח, הח
לפרטים נוספים
חומרה
Job Description:
In charge of planning (architecture) and developing (coding) all the needed
simulation environments for tests and debugs.
The simulation environments are used to develop new RTL blocks, Full-chip
integration, FPGA code and also to debug and resolve bugs found.
Job Requiremen
In charge of planning (architecture) and developing (coding) all the needed
simulation environments for tests and debugs.
The simulation environments are used to develop new RTL blocks, Full-chip
integration, FPGA code and also to debug and resolve bugs found.
Job Requiremen
לפרטים נוספים
חומרה
דרישות:
· תואר ראשון במדעי המחשב / הנדסת חשמל - חובה
· נסיון של 5 שנים לפחות בהגדרה ומימוש
סביבות ווריפיקציה בסביבות Specman / eRM or
SystemVerilog / UVM- חובה
· נסיון בוריפיקציה ל-ASIC - חובה
· כישורי תקשורת ועבודת צוות טובים – חובה
· יצירתי/ת, ראש גדול, בעל/ת כישרון טבעי
לאיתור באגים
· תואר ראשון במדעי המחשב / הנדסת חשמל - חובה
· נסיון של 5 שנים לפחות בהגדרה ומימוש
סביבות ווריפיקציה בסביבות Specman / eRM or
SystemVerilog / UVM- חובה
· נסיון בוריפיקציה ל-ASIC - חובה
· כישורי תקשורת ועבודת צוות טובים – חובה
· יצירתי/ת, ראש גדול, בעל/ת כישרון טבעי
לאיתור באגים
לפרטים נוספים
חומרה
Architecture and implementation of SW tools for DSP/ CPU hardware
development.
The job involves designing, programming, simulating and testing automated
processes.
REQUIREMENTS
5+ years of experience in software development (C/ Python)
Proficient understanding in full-cycle of software developmen
development.
The job involves designing, programming, simulating and testing automated
processes.
REQUIREMENTS
5+ years of experience in software development (C/ Python)
Proficient understanding in full-cycle of software developmen
לפרטים נוספים
חומרה
Position summary:
Develop verification definitions for various products.
Take part in overall chip level coverage based verification work .
Analyze and review product specifications for building related verification
plans.
Position Qualifications:
BSc in Electrical Engineering, from a well-kn
Develop verification definitions for various products.
Take part in overall chip level coverage based verification work .
Analyze and review product specifications for building related verification
plans.
Position Qualifications:
BSc in Electrical Engineering, from a well-kn
לפרטים נוספים
חומרה
Own tasks of ASIC verification
-Develop test environments in System Verilog
-Create verification plans
-Debug ASIC designs
-Integrate unknit level environment for full chip
-Participate in design reviews
-Collaborate with your peers in the architecture, design and SW teams
-3+ years of
-Develop test environments in System Verilog
-Create verification plans
-Debug ASIC designs
-Integrate unknit level environment for full chip
-Participate in design reviews
-Collaborate with your peers in the architecture, design and SW teams
-3+ years of
לפרטים נוספים
חומרה
Technical Profile:
BSc degree in Electronics and Electrical Engineering
At least 5 years working experience in pre silicon verification
Strong knowledge and experience in pre silicon Verification flow, from
defining test plan, coverage plan, toward implementation of the
verification envi
BSc degree in Electronics and Electrical Engineering
At least 5 years working experience in pre silicon verification
Strong knowledge and experience in pre silicon Verification flow, from
defining test plan, coverage plan, toward implementation of the
verification envi
לפרטים נוספים
חומרה
Work with multi-disciplinary teams (local and international) in various
areas:
SW/FW Development
RTL Design
Design Verification
System Architecture
Modem Architecture
Develop HW Architecture specifications for Modem IPs and subsystems
Drive projects execution in VLSI, SW, FW, Pre/Post Silicon acti
areas:
SW/FW Development
RTL Design
Design Verification
System Architecture
Modem Architecture
Develop HW Architecture specifications for Modem IPs and subsystems
Drive projects execution in VLSI, SW, FW, Pre/Post Silicon acti
לפרטים נוספים