Definition, architecture, and development of verification environments using mature proven verification flow, with SystemVerilog/UVM methodology
Definition and development of block-level and IP-level environments, integrated and reused in full-chip environments
• Education: graduate or student (4th year)
Computer or Electrical engineer (BSC)
• Graduate or 4th year student
• Experience with system-verilog/verilog is an advantage
• Ability for self-learning, with high enthusiasm to learn
• B.Sc. in Computer / Electrical engineering with a grades above 80 from a well-known institute
• At least 5 years' experience as ASIC verification engineer
• Deep knowledge in system-Verilog / UVM methodology.
• Deep knowledge in RTL debugging
• 2-4 years experience (at least)in design verification.
• Coding: System Verilog vmm/uvm, Verilog, perl.
• Experience in coverage and in block closure.
• BSc. in Electronic Engineering, Computer Science or Computer Engineering
• At least 5 years’ experience as formal verification engineer
• Knowledge of Hardware formal verification concepts and tools, Jasper is an advantage
job description requirements:
a. At least BSc. In EE.
2. Proven experience in leading a small to medium size DV team (3-7 people) for a significant time including:
a. Team mentoring.
b. Environment / Test plan definition and development.
3 years of experience in HW Verification developing, methodologies and implementation.
Experience in building a test plan and setting verification goals
Experience and understanding of Random Verification concepts, methodologies and Environments
BSC in Electrical Engineering – from a well-known university
At least 4 years' experience
Knowledge in specman - an advantage.
Knowledge in uvm – an advantage.
Job Description :
Tools group is responsible for developing FPGA based solutions to verify the memory products of the company.
. Developing top level/module level test using Specman
. Developing top level SW test
. Writing SW for HW/SW emulation
S e m I c o n d u c t o r Company in the North is looking for a verification engineer. The job requirements are:
B.Sc. / M.Sc. in Computer Engineering.
At least 5 years experience in chip design and verification.
• Be a significant part of the MAC/SoC Silicon Verification team.
• Investigate, invent, develop, innovate and improve challenging verification environments in a full-chip platform.
Be part of a Highly skilled, energetic team developing the next generation high - end Embedded SOCs and Communication SOCs for the networking industry.
Take ownership of Design Definition and Implementation.
Interact with IP teams/vendors to resolve technical issues.
B.Sc in electrical/communication engineering, computer science or equivalent.
Passion for SW, HW platforms, networking and cutting edge technologies
Self-learner, able to understand specifications and able to perform a complex task on his own
- B.Sc. in Electrical engineering/Software engineering.
- At least 5 years of experience in digital verification.
- Deep understanding of verification tools and methodologies – A must.
- At least 3 years of experience in UVM and system verilog – a...