{[{title}]}
חומרה
Leading the Chip Design project, including direct management of the VLSI team
members (Design, Verification, FPGA).
Job Description
As a manager, set priorities for the team, get results across boundaries,
ensure an inclusive work environment, develop employees, and manage
performance.
Driv

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Senior VLSI Designer

113039
Responsibilities:• Handling RTL design for new blocks and legacy blocks,
chip integration, block level and top level verification, RTL simulations and
gate level simulations.• Close work with architecture and system groups for
design specification definitions and implementation impacts.• Block le

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Job Description:
• Developing BackEnd flow using Cadence and Synopsys tools
• Implementation of ASIC units using advanced flows
Job Requirements:
• 4+ years experience with RTL2GDS flow
• Knowledge of Cadence and/or Synopsis tools
• Script writing skills with TCL /python /sed/awk
• Experience with s

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BSc. in Electrical Engineering
 Minimum 2 years of experience – Must!
Knowledge and experience in:
• Floor plan and Place & Route
• Timing Closure & debug, STA
• Clock Tree Synthesis
• Power Grid Analysis
• LVS/DRC debug
• Experience with DFT - Advantage
• Experience with ICC – Advantage

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Experienced Back End Engineer

113035
 Job Description:
•Developing BackEnd flow using Cadence and Synopsys tools
•Implementation of ASIC units using advanced flows  
 Job Requirements:
•4+ years experience with RTL2GDS flow
•Knowledge of Cadence and/or Synopsis tools
•Script writing skills with TCL /python /sed/awk
•Experience with sig

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Experienced Backend Engineer

114398
The position includes the following responsibilities:
 -          RTL to GDS full flow (synthesis, Place & Route)
 -          Signoff flows (Timing signoff,  DRC & LVS signoff)
 -          Post – silicon correlation and characterization
  
 The job require close and interactive work with other group

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Design Engineer for VLSI team

110535
The job will include :
• Handling RTL design for new blocks and legacy blocks,
• Supporting chip integration
• Involvement in Block level synth, CDC, lint, integrating and supporting
DFT structures.
• Support BE team and Verification team during chip implementation for
design related topics as

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