The job will include :
• Handling RTL design for new blocks and legacy blocks,
• Supporting chip integration
• Involvement in Block level synth, CDC, lint, integrating and supporting DFT structures.
• Investigate, develop, innovate and improve challenging Physical Design flows.
• Multi-disciplinary, Participating in many steps of the Physical Design flow. Escorting the design from RTL to GDS.
• Developing BackEnd flow using Cadence and Synopsys tools
• Implementation of ASIC units using advanced flows
BSc. in Electrical Engineering
Minimum 3-4 years of experience – Must!
B.Sc. in Electrical Engineering (Electronics) / Computer Engineerin
8+ years of experience as ASIC Back-end engineer
3+ years of experience as a Back-End team leader
Experience in advanced CMOS process nodes (double patterning )
HW development engineer
• Analog and digital board design of power/energy measurement equipment, including analog signal measurements, power supply, CPU environment, communication modules, etc.
A hi-thech copmpany in the north looking for a Chip Design Engineer
• Development of mini-architectural of major modules in the IC, design & verification.
• Drive the process of RTL design and debug.
Senior Chip Design Manager
Leading the next generation state of the art Satellite SoC activity through the full life cycle: from architecture to design and until production. Drive to completion of projects on time and within budget. Including methodologies and tool...
- 1 years experience in physical design of large scale SoC
- Extensive experience with one of the place & route tools available today (Synopsys / Cadence). Familiar with hierarchical design approach, top-down design, timing and physical convergence