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חומרה

Experienced VLSI Design Engineer

833503
As part of this position you will work on a full design flow from
architecture definition, through micro ARCH, Verilog writing and verification
process up to timing closure and STA. 

Requirements   

B.Sc. / M.Sc.

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ASIC backend Engineer

522757
 looking for an ASIC Backend engineer to join its Chip Design team!
As a Backend engineer, you will take a significant part of the full chip
development flow, from RTL to GDS.
You will be responsible for Synthesis, Floor Planning, Place & Route, STA,
DFT architecture and more. 
Requirements:  

BS

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Hardware & FPGA Engineer

146147
 Job Description (or: What Will Your Job Look Like?) 
· You will be a part of a new project design team in a multidisciplinary
company. 
· Logic design of sophisticated blocks with Xilinx technology (FPGA
and SOC in VHDL) 
· Responsibility for successful integration of a data path board with
other d

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For an exciting well-funded start-up, we are looking for a Backend Team
member.
The company founders have demonstrated an impressive record of exits and
delivery.

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Requirements: 



BSc in Electrical/Computer Engineering. 
More than 3 years of experience as Physical Design engineer. 
Experience in Synthesis and Implementation. 
Advantage is knowledge in: DFT, DRC, LVS, LEC, Power. 
Advantage for Cadence tools experience. 
Thinker, team player and motivated.  

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Design Engineer for VLSI team

110535
The job will include :
• Handling RTL design for new blocks and legacy blocks,
• Supporting chip integration
• Involvement in Block level synth, CDC, lint, integrating and supporting
DFT structures.
• Support BE team and Verification team during chip implementation for
design related topics as

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Physical design lead

471267
Physical design lead with experience in advanced nodes implementation of unit
level and Full chip and methodologies
in her/his role will require to build full flow which include synthesis , P&R
and signoff , execute unit level and full chip implemetation 
Advantages: working with ASIC vendors

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2-3 years experience with RTL 2 GDS flow 
Experience with 2 or more full SoC cycles; taking the design from the RTL
phases to GDSII. 
Knowledge of Full Flow Cadence and/or Synopsis tools (both flows –
advantage). 
Excellent debugging skills 
Script writing skills with TCL/Python/SED/AWK  

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Job Description:
• Developing BackEnd flow using Cadence and Synopsys tools
• Implementation of ASIC units using advanced flows
Job Requirements:
• 4+ years experience with RTL2GDS flow
• Knowledge of Cadence and/or Synopsis tools
• Script writing skills with TCL /python /sed/awk
• Experience with s

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