BSc in Electronics engineering/communication system engineer/ Computer Engineering from a leading University.
Looking for outstanding Engineers to join the development of new Wi-Fi and Automotive SoC products.
The job will include :
• Handling RTL design for new blocks and legacy blocks,
• Supporting chip integration
• Involvement in Block level synth, CDC, lint, integrating and supporting DFT structures.
• Education: graduate or student (4th year)
Computer or Electrical engineer (BSC)
• Graduate or 4th year student
• Experience with system-verilog/verilog is an advantage
• Ability for self-learning, with high enthusiasm to learn
השכלה: B.Sc בהנדסת חשמל /אלקטרוניקה ממוסד אקדמי מוכר.
5 שנות ניסיון ומעלה בפיתוח וכתיבת קוד עבור מודולים דיגיטליים ב-Verilog / System Verilog.
• Micro-architecture (Definition)
• Circuit design
• Digital Verification
• FPGA/ASIC design, doing the full cycle from architecture, through design and integration, and up to customer deployment.
• Logic design, verification, synthesis and physical implementation.
Our Chip Design department is looking for brilliant VLSI Design Engineers to join the team!
In this role you’ll take part of RTL coding of new IPs and SoC integration.
you will have responsibilities of top level and/or complex blocks of a SOC, across all phases of Front-End design, including micro-architecture specification, RTL code development, debug of complex logic in high performance, and low power design.
Block owner in a WiFi chip set including micro-architecture and logic design.
• BSc. in Electrical/Communication/Computer engineering from university - Must.
• experience in Frontend design – Must
• Familiarity with RTL to GDSII full flow implementation – Advantage
• Backend experience - Advantage
• Knowledge in Verilog and System Verilog
• System view oriented – manages to see the full picture
• Integration experience - advantage
• Good understanding of Networking and the switching packet walk through - advantage
• Experienced security architect working with both external and internal parties on security architecture of future company products.
• Review of external chip vendors’ security architecture
A hi-thech copmpany in the north looking for a Chip Design Engineer
• Development of mini-architectural of major modules in the IC, design & verification.
• Drive the process of RTL design and debug.
Senior Chip Design Manager
Leading the next generation state of the art Satellite SoC activity through the full life cycle: from architecture to design and until production. Drive to completion of projects on time and within budget. Including methodologies and tool...
• Experience of 3 years in RTL design and/or micro-architecture, preferably of networking silicon such as NIC, Switch
• Knowledge of Verilog, logic design principles along with timing, area and power implications