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חומרה

SOC ASIC Design Engineer

116845
Responsibilities:
Take part in all aspects of digital design – from architecture and
specification, RTL design and verification
Close collaboration with the Physical Design team, and supporting SW and
Production teams.
Contribute to the development of a very complex state-of-the-art
technological

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Key Qualifications
VLSI design experience in SoC for consumer applications – an advantage
Familiar with the various backend tools (synthesis and STA)
Familiar with advanced design practices (Clock/Voltage domain crossing, DFT
and Low Power Design)
Familiar with verification methodologies
Strong Ver

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you will have responsibilities of top level and/or complex blocks of a SOC,
across all phases of Front-End design, including micro-architecture
specification, RTL code development, debug of complex logic in high
performance, and low power design.

Requirements:
2-4 years hands-on RTL coding in

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BSc in Computer science/ Electrical engineering from known University –
Must.
 8+ years of experience in VLSI design – Must.
 At least 3 years of experience as team leader or team manager – Must.
 Deep knowledge in Verilog – Must.
 Experience in micro-architecture and design of complex blocks – Mus

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חומרה

Senior VLSI Design Engineer

113523
VLSI design engineer that will join our team. Taking part in
micro-architecture, design, IP integration and other tasks as part of the
chip development processes.

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Digital Design Engineer

116798
What will you do?
Work with cross-functional teams to develop hardware architecture for next
generation systems.
Design, implement, debug and characterize embedded systems.
Lead new design concepts through exploration, prototyping, development, and
into mass production.
Collaborate with other team

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Required skills & experience:
• Engineering degree
• Minimum of 3-5 years experience of ASIC and/or FPGA development
• Good experience of Verilog/VHDL
• Knowledge of synthesis and static timing analysis tools would be a bonus
• Experience of implementing digital signal processing modules would be a

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Classic VLSI engineers
VLSI designers with 5-10 years of experience, hands on
Front end  
 

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Micro-Architect & RTL Design Engineer

115049
As part of your role you will:
Own HW design tasks.
Define, Design and implement HW solutions.
Work closely with DFT, Backend and verification teams.
Collaborate with your peers in the architecture, SW and System teams.
 
Key requirements:
EE from a known university.
3 years and more of hands-on exp

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For our Remote PHY Full Duplex chip, We look for talented, highly qualified
Design engineer:
• Education Bsc in Electrical Engineering
• Experience in PHY, DSP And Digital Communication
• Experience in writing RTL for Modem
• Experience in reading standards and come with the optimal
Architecture/I

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Job Description
Lead  the VLSI development of a novel massively parallel processor
architecture. This is a technical, hands-on management role.

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SENIOR VLSI ENGINEER

116500
Job Requirements:
 
B.Sc. in Computer / Electrical engineering with grades above 80 from a
well-known institute
At least 7 years of VLSI front end design experience
Ability to define block micro-Architecture under system-level requirements
Experience with ASIC synthesis and STA flows
Fast learning...

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Hardware Design & Verification

115558
Job Description:• Design AI modules for high-speed neural network
training• Develop verification environment and
tools• Design-for-testability• Identify and solve performance bottlenecks
Skills:• Experienced VLSI designer ASIC/FPGA• Familiar with Verilog, UVM,
Python• Hands-on !• B.Sc.

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Minimum Qualifications
  
2+ years of related work experience.
Knowledge in digital design techniques, preferably from the field of ASIC
design front end activities.
Ability to work in a team.
Ability to understand system wise aspects like interaction of HW with SW and
FW.
Ability to create digita

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חומרה

Senior VLSI Designer

113039
Responsibilities:• Handling RTL design for new blocks and legacy blocks,
chip integration, block level and top level verification, RTL simulations and
gate level simulations.• Close work with architecture and system groups for
design specification definitions and implementation impacts.• Block le

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