תאריך עדכון | 12/03/2020 |
תיאור המשרה | BSc in Computer science/ Electrical engineering from known University – Must.
8+ years of experience in VLSI design – Must.
At least 3 years of experience as team leader or team manager – Must.
Deep knowledge in Verilog – Must.
Experience in micro-architecture and design of complex blocks – Must.
Familiar with the verification process of a block (test plan, coverage, etc.) – Must.
Excellent communication skills in English (written and verbal) – Must.
Experience with multi-clock domain designs – Advantage.
Script knowledge (TCL, Perl, etc.) – Advantage.
Experience with chip frontend process (synthesis/STA) – Advantage.
Strong execution orientation.
Thorough and accurate.
Good communicator and team player.
Fast leaning skills.
Open minded.
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