VLSI Front-End Engineer

Minimum qualifications:
3+ years in digital design/verification/implementation and Front-End ASIC flows (RTL coding, simulation, synthesis)
Familiarity with Verilog/Sys-Verilog  HDL languages
Familiarity with UNIX development environment
Experience in FE implementation tools
Synthesis (preferred synopsys DC/DCG)
Timing constraints writing and analyzing
Equivalent checks (like LEC)
Static timing analysis (preferred synopsys PTPX)
Very Good communication skills (job requires working with multiple different teams)
Very good verbal and written English
 
Preferred qualifications:
Experience in UPF synthesis flows
Experience in Back-End flows and tools
Experience in DFT and memory BIST flows and tools
Familiarity with UPF/CPF standards and low power flows/tools
Knowledge in script writing in Python/Perl/Tcl
Experience in signal processing design and standards  
 
Required: Bachelor’s, Computer Engineering and/or Electrical Engineering