participate in developing VLSI for PON SOC products of broadband fiber access systems.
Oversees definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system simulation. Responsible for and contribute to the development of multidimensional designs involving block and chip level. Evaluates all aspects of the process flow from high-level design through synthesis, DFT, timing, and power.
Requirements:
– BSc in EE with a minimum of 12 years of experience in similar roles
– Must have a working knowledge, and skills in one or more of the following disciplines/tools: Synthesis flow, STA flow, SOC integration flow, DFT flow, Spyglass EDA, CDC, DFT, LINT, LEC, SoC frontend design flow
– The candidate must have excellent written and verbal communication skills
