VLSI developer with high experities in developing designs for complex SoC devices, from definition to coding and verification.
Hands on, strong engineer, responsible, motivated and innovator. Understand the full design and system view.
Verilog and SystemVerilog knowledge.
Responsible for block level synth, lint, integrating and supporting DFT structures.
Experienced in Networking architecture and protocols (Ethernet, TCP/IP, RDMA)
Experienced in block designs for High-speed network devices (Like: NIC, NPU, Traffic Manager, Switches)
Advantage for the following:
– Leading VLSI teams/projects
– Verification experience and knowledge with SV/UVM
– CPU subsystem & Multi-core designs experience
– Experience with Synthesis and STA analysisVLSI developer with high experities in developing designs for complex SoC devices, from definition to coding and verification.
Hands on, strong engineer, responsible, motivated and innovator. Understand the full design and system view.
Verilog and SystemVerilog knowledge.
Responsible for block level synth, lint, integrating and supporting DFT structures.
Experienced in Networking architecture and protocols (Ethernet, TCP/IP, RDMA)
Experienced in block designs for High-speed network devices (Like: NIC, NPU, Traffic Manager, Switches)
Advantage for the following:
– Leading VLSI teams/projects
– Verification experience and knowledge with SV/UVM
– CPU subsystem & Multi-core designs experience
– Experience with Synthesis and STA analysis