חומרה

Verification Technical Lead Engineer

662961

תאריך עדכון

27/12/2020

תיאור המשרה

Responsibilities

• Definition, architecture, and development of verification environments and verification flows, with UVM like methodology using either Python or System Verilog.

• Definition and development of block-level and IP-level environments, integrated and reused in full-chip environments

• Determines verification methods and procedures on assignments for all team members

• Work closely with experienced design, software and algorithm teams

Requirements

• BSc/MSc in Electrical Engineering or Computer Engineering

• At least 5 year experience in functional verification

• At least 3 year experience with Python or SystemVerilog/Specman UVM

• Good knowledge of coverage-driven verification flow

• Proven track record in verification work. This includes planning, execution, tracking, verification closure

• Team Player, able to coach and mentor other team members

• Strong analytical and problem-solving skills

Preferred Qualifications

• Experience in verification of SoC level / Full chip level

• Experience in working with VIPs

• Experience in verifying algorithmic /mathematical design (Image processing, filters) 

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