Join a verification team responsible for the verification of state of the art networking ASIC designs. As part of the verification effort, new and advanced re-use methodologies are used. Full verification flow - block-level to sub-chip and full-chip benches, formal verification and much more.
• Good interpersonal skills (initiative, leader, open minded)
• Must have an engineering degree in EE/CS from a well-known university
• Must have experience in ASIC Verification using one of the following HVLs: Specman , SystemVerilog
• Must have experience with advanced verification methodologies (constraint random, coverage oriented, verification reuse) as UVM , eRM, VMM, OVM
• Good knowledge in Verilog HDL - an advantage
• Experience with scripts tools as Perl and TCL - an advantage
• Knowledge in Ethernet /PCIE - an advantage