Verification and Validation manager

Job Responsibilities:
Lead the WW Verification activities and direct manage 8+ talented DV +AVV engineers.
Design verification architecture sole ownership, defining the DV requirements for full signoff on SoC from architecture stage to tapeout.
Close collaboration with System, architecture , Design , FW teams.
Driving DV innovation on emerging technologies to constantly improve efficiency.
Define, design, implement and debug verification environments and tests for cutting edge wireless products.
Deep dive into both low level and system level modules.
 
Requirements:
graduate of  B.Sc. or M.Sc. in electrical/communication engineering, computer science or equivalent.
Proven Managing  experience , leading a team for at least 2 years. At least 5 years of proven  experience In verification.
Wide experience in verification languages and methodologies – SystemVerilog and/or Specman, UVM.
Passion for complex HW and SW platforms, networking and power management in cutting edge technologies .
Self-learner, able to understand specifications and able to own and perform a complex tasks end to end.
Ability to work in a team both local and global