SW Engineer

Must:
• BSc in CS from a leading institute
• 2-5 years of hands-on SW development experience in an industrial setting.
• Well versed in object-oriented design, SystemC/C++ programming experience is a plus.
• Good communication skills, excellent inter-personal skills.
 
Advantage:
• Knowledge and experience in Verilog/SystemVerilog.
• Emulation experience on Palladium
• Familiarity with different communication protocols.
• Familiarity with UVM methodologies.
• Familiarity with Compilation flows and scripting.