You are:
A team player with good communication skills, enjoying the work with architecture, verification, system & SW teams
Passion to mentor younger teammates
Innovative, able to take a block from scratch throughout the design process
You will:
Be responsible for RTL design of new blocks (from scratch) as well as legacy blocks enhancements
Solve low-power challenges, in a challenging algorithmic design
Mentor younger engineers with your design experience
Work in a multi-disciplinary environment, including architecture, verification, system & SW groups for design specification definitions and implementation
Handle block-level synth, lint, integrating and supporting DFT structures
Support BE team during chip implementation for design-related topics as well as production and validation team tests ramp-up
Position Requirements:
You hold a bachelor’s degree in Electrical Engineering or Computer Engineering
You have at least 6 years of experience as a design engineer
You hold wide and deep experience in design – preferred with low-power techniques, synthesis, sta analysis, power analysis, and formal tools such as lint & CDC
You are experienced with Verilog design advanced techniques
You hold knowledge of AMBA fabrics, DFT techniques, BISTS, and memory handling- Advantage
You must be fluent in English