· RTL ownership: Development, assessment and refinement of RTL design to target power, performance, area and timing goals
· Performance exploration and correlation: Explore high performance strategies and validate that the RTL design meets targeted performance
· Design delivery: Work with cross-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power
Requirements
· B.S. degree in electrical engineering
· 7+ years of directly relevant experience
· Knowledge of chip architecture
· Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools
· Knowledge of logic design principles along with timing and power implications
· Understanding of low power design techniques
· Understanding of high-performance techniques and trade-offs
· Experience with Design for Test concepts and flows
· Ability to generate Verilog models for use by top level simulation environment