• Logic design engineer that will join the Digital Solutions group.
• Taking part in the architecture and implementation of complex Networking IPs, MAC layer and SoC design.
• Working closely with the system team, developing together high end DSP and Networking IPs.
• Responsible for the correctness and deployments of the IP.
• Communicating, when require, with external vendors.
• B.Sc in Computer Science/ Electrical Engineering - Must.
• Strong background in networking, communications protocols and/or signal processing - Must.
• At least 5 years' experience as VLSI/FPGA Design Engineer with Veriog - Must.
• Strong system understanding - Must.
• Experience with FPGA synthesis, timing closure and/or ASIC flow.
• FPGA and complex system debugging experiense.
• Experienced in implementation of complex communication IP – Advantage.