•5+ years of experience in hand on FPGA Design.
•Experience of RTL design with Verilog, VHDL or SystemVerilog.
•Experience of bringing up and debugging FPGA based HW and FW.
•Experience developing and implementing FPGA-optimized versions of DSP algorithms.
•Familiarity with modern Xilinx FPGA and SoC families and design tools (7-series FPGAs, Ultrascale+, Zynq-7000, Ultrascale Zynq, RFSoC, Vivado, Xilinx IP cores). Preferred Qualifications:
•Experience with multiple high-speed serial communication standards and interfaces (e.g. Aurora, 10Ge, PCIe, DDR4/3, JESD204B).
•Experience with standard internal interfaces such as AXI4, AXI4-Stream, AXI4-Lite.
•Experience working with SoC designs such as Zynq and Zynq Ultrascale+ including architecting and interfacing with peripherals, interrupts, and related bus architectures.
•Familiarity with Xilinx Vivado and SDK as well as 3rd party logic simulators.
•Scripting and modeling: Python, Tcl, Perl, C/C++.