Senior Formal verification Engineer

• BSc. in Electronic Engineering, Computer Science or Computer Engineering
• At least 5 years’ experience as formal verification engineer
• Knowledge of Hardware formal verification concepts and tools, Jasper is an advantage
• Solid understanding of formal verification technologies and abstraction techniques.
• Hand on script knowledge
• Ability to lead technical activities
• Strong Independent and collaboration skills
• Knowledge in verification methodologies, tools, and techniques
• Knowledge of Verilog or VHDL, System Verilog