The job will include:
- Handling RTL design for new blocks and legacy blocks.
- Supporting chip integration.
- Involvement in Block level synth, CDC, lint, integrating and supporting DFT structures.
- Support BE team and Verification team during chip implementation for design related topics as well as production and validation teams tests ramp up.
- 5 years’ experience as VLSI front-end engineer.
- Creativity and out of the box thinking
- Experience with Verilog design coding. (System Verilog design is a plus)
- Experience with legacy code understanding, debugging and problems solving attitude
- Have advanced knowledge of SoC architecture/design
- Good communication & teamwork skills
- Preferred Qualifications
- System Verilog design is a plus
- Leadership experience - Advantage
Required: Bachelor's, Electrical Engineering or equivalent experience