You are:
· People person with excellent communication skills (job requires working with multiple different teams).
· desire to explore and reach new territories and goals
You will:
· Create time constraints for functional and test modes
· Perform synthesis for digital designs
· Develop Floorplan
· Perform PnR including CTS, STA and signoff
· Develop Hard Macro block RTL to GDSII
· Create and implement UPF for multiple voltage domains designs
· Integrate Analog or RF blocks LIB, LEF, GDS
· Support other Chip Backend, Design and Power teams along the project.
Position Requirements:
· You hold BSC in Electrical Engineering or similar
· You have at least 4 years of proven experience in RTL to GDSII or an expertise in 2 of the main Backend digital disciplines (Synthesis, PnR including CTS, STA and signoff)
· You are familiar with Verilog/System-Verilog HDL languages.
· You are familiar with UNIX development environment.
· You have incredible professional knowledge in Front-End ASIC flow
• You must be fluent in English
It will also be nice if:
· You have Knowledge in script writing in Python/Perl/Tcl.
· You are familiar with Synopsys full BE Flow.
· You are familiar with UPF/CPF standards.
· You are familiar with power estimation tools (like PTPX/Power Artist).
· You are familiar with power static verification tools (like CLP).
· You have actual Design experience in Verilog Or System-Verilog.
· You have knowledge in layout verification (LVS/DRC) and/or in analog, IOs or Circuit Design
