חומרה

RTL Design PROJECT LEADER

947783

תאריך עדכון

22/11/2020

תיאור המשרה

Requirements:

· BSc. in Electrical Engineering (from known university)

· Minimum 8 years of experience – Must!

Must have extensive experience in:

· Logic design project leader or chip architect

· Hands on RTL design with Verilog or System Verilog

· Micro architecture definition in CPU/DSP environment

· Knowledge in verification (System Verilog, System-C etc.) Knowledge and experience in the following is advantage:

· RTL for FPGA and emulation

· AC spec definition

· SDC timing constraints write from spec

· RT C, C++ ,assembly

· Experience with SOC design in DDR, USB, MIPI, ARM subsystem, AMBA, AXI, AHB, DSP, and ARC

· Hands on spyglass, synthesis, STA, DFT

· Experience with technical customers support or interface 

שלח קורות חיים
המשרה מיועדת לנשים ולגברים כאחד