Buliding blocks and architectures
Responsible for simulation and achieving the result on silicon
3+ years in developing RFIC.
RF transceiver system knowledge (link budget)
Bluetooth, Wi-Fi, LTE radio knowledge - advantage.
RFIC sub blocks experience (such as LNA, PA, VCO)
Expert in Cadence Virtuoso tool-suite or alike.
Experience in design for mass production and high volume.
Solid lab experience
leading less experience RFIC designers in their tasks.
Education: Masters EE strongly desired.