Principal Logic Design Engineer

• Own or participate in the definition, design, verification, and documentation for digital logic systems on integrated circuits. This includes developing architecture, module interfaces, and design approaches. 
• Architecture and Definitions: Converting customer and product requirements into detailed design goals to be used in implementation.
• RTL ownership: Development, assessment and refinement of RTL design to target power, performance, area and timing goals
• Validation: Support test-bench development and simulation for functional and performance verification
• Performance exploration and correlation: Explore high performance strategies and validate that the RTL design meets targeted performance
• Design delivery: Work with cross-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power
Requirements
• B.S. degree in electrical engineering
• 15+ years of directly relevant experience
• Thorough knowledge of chip architecture
• Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools
• Knowledge of logic design principles along with timing and power implications
• Understanding of low power design techniques
• Understanding of high-performance techniques and trade-offs
• Hands on experience in logic synthesis and integrating RTL driven logic into the full chip
• Experience with Design For Test concepts and flows
• Experience with memory BIST generation and usage for embedded macros
• Ability to generate Verilog models for use by customers in their simulation environment