Estimate and analyze power consumption of VLSI products pre and post silicon.
Develop and maintain power related physical design flows, as part of technology team.
Responsibility on power optimization for all stages – RTL to GDS.
As part of PD team – perform physical implementation of various ASIC/SoC VLSI designs:
The physical design includes RTL to GDS flows: synthesis, floor-planning, PnR, power grid distribution, clock distribution, Power Integrity and EM analysis, Static Timing Analysis and closure, logic/physical ECO implementation, formal verification, Signal Integrity and Xtalk analysis.
Close and interactive work with other groups such as architecture, logic design, DFT, testing and production teams.
B.Sc. in Electric Engineering / Computer Engineering.
3+ years of experience in VLSI physical design.
At least 1 year of experience in digital power estimations, planning and analyzing.
Scripting and programming experience.