Physical Design / Backend Engineer

· B.Sc./M.Sc. in Electrical Engineering with high GPA 
· >4 years of experience with RTL2GDS flow (ICC2/Innovus) with STA closure  
· >3 years of experience in Full Physical verification flow (DRC/LVS/DFM) with ICV/CALIBRE 
· >2 years of experience in Developing BackEnd flow and methodologies with Cadence or Synopsys tools. 
· Checking and performing IR-drop, ESD & Electromigration analysis  
· Script writing skills with TCL/python/sed/awk 
· Basic knowledge in Structural Design (Synthesis, Timing closure, Formal Equivalence Check) – an advantage 
· Low Power Design including Power intent (UPF) definition & verification – an advantage. 
· Experience in RTL blocks design (Verilog/VHDL) – an advantage  
 
Personal Profile:
·  Excellent communication skills
·  Team player
·  Multitasking, self-motivated, and problem solver
·  High level English (read, write, speak)