חומרה

Junior Verification Engineer

116951

תאריך עדכון

19/11/2019

תיאור המשרה

What will you do?
    • Responsible for the full life cycle of verification, from verification planning to test execution, to collecting and closing coverage.
    • Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
    • Create a constrained-random verification environment using SystemVerilog.
    • Identify and write all types of coverage measures for stimulus and corner-cases.
    • Debug tests with design engineers to deliver functionally correct design blocks.
    • Collaborate closely with design and verification engineers in active projects and perform hands-on verification.
    • Close coverage measures to identify verification holes and to show progress towards tape-out.
 
 
    • BSc. in Electronic Engineering MSc. an advantage
    • Knowledge in verification methodologies, tools (simulators and relative APIs, coverage tools, accelerators, formal, etc.), and techniques
    • Knowledge of Verilog or VHDL, System Verilog
    • Experience in C and Perl programming
    • Good knowledge of UNIX environment and script languages
    • Methodological approach to building of verification environment and test plan
    • Methodological approach to the verification tasks planning and execution
    • Documentation skills
 
 
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