IP Design and integration Leader

Responsibilities:
Design lead for digital ASIC chips.
Define hardware specification and Micro Architecture.
Execute top level integration of complex SoC designs.
Work closely with physical design team to optimize implementation and meet design constrains.
Define and implement DFT Architecture.  
 
Requirements:
B.Sc./M.Sc. in Electrical Engineering from a leading university.
At least 5 years of experience in complex ASIC design.
At least 2 years of experience as technical leader/team leader.
Proven record of ASIC tape-outs as full chip integrator/design lead.
Proficiency in synthesis and STA tools.
Experience with ATPG, MBIST tools.