Requirements:
5 years of FPGA design experience, preferably AlteraFPGAs.
Experience with going through several Iarge FPGAs – complete design cycle, from RTL to timing driven synthesis to place & route, static timing analysis.
5+ years of RTL, Verilog / SystemVerilog,
Preferred Skills:
Expertise with Synplify, VCS, Verdi
Experience with NIOS uController
Familiarity with USB / DisplayPort / CSI protocols
Hands on experience with debug tools – Logic analyzer, scope etc.