- Bsc. In electrical engineering / Computer science from known university
- 3+ years of experience in of FPGA or ASIC design, verification and implementation.
- Knowledge in the following languages:
- Verilog, VHDL
- System Verilog
- Perl, Python
- Familiarity with Vivado and Questa - an advantage
- Experience in advanced verification methodologies using SystemVerilog / Speman coverage driven and direct tests - an advantage