Formal Verification Engineer

 The Verification Cmos-Image-Sensor-Team is required to tackle the full flow of verification, from block & IP level to system level, including interfaces & deep understanding of all design flow and technical teams (such as Digital & FW). 
We are looking for people with a broad set of technical skills, who are ready to tackle some of technology’s greatest challenges, who have the ability to think out of the box and bring the disruptive technologies that will define our future. 
Experienced Formal Verification engineer with over 3 years of related professional experience. 
Advanced knowledge of digital logic design process and verification techniques. 
Advantage  
Experience with Jasper Platform  
Scripting Proficiency in TCL/Perl/Python