חומרה

Formal Verification Engineer

113576

תאריך עדכון

28/05/2019

תיאור המשרה

Job Description:
Planning and developing all the needed Formal activities.

Job Requirements:
BSC in Electrical Engineering – from a well-known university
At least 2 years’ experience as formal verification engineer
Knowledge in Verilog is a must.
Knowledge in standard verification – an advantage

שלח קורות חיים
המשרה מיועדת לנשים ולגברים כאחד