Job Description
• Understand the existing FPGA architecture and interactions between the various modules comprising the system.
• Conceive, experiment with, and present modular architectural approaches for FPGA applications with high emphasis on testability.
• Work closely with software, hardware, system teams, providing documentation, debug support, technical expertise and software interfaces
• Develop RTL code for additional functionality and capabilities. Perform logic synthesis, timing analysis and timing closure.
• Develop test bench and simulation tools to verify correct logical functionality.
• Understand schematics, performing lab test on designs and components, troubleshooting and improving building block modules.
Requirements
• BS/MS in Electrical Engineering, Computer Science or related area
• Over 5 years of experience designing FPGA in VHDL or Verilog.
• Practical knowledge of RTL design, synthesis, timing closure, simulation and verification test benches
• Hardware bring up and debug experience desired
• Expertise in FPGA from Xilinx/Intel (Altera) families.
• Familiarity with high level programming languages f.e C/C++, System Verilog, High Level Synthesis, Scripts (TCL, Python) – big advantage
• Familiarity with AXI methodology
• Familiarity working with verification engineers using UVM environment
• Ability to work in a team and take input from other members in coordinating work
• Ability to prioritize work assignments and react to a dynamic work environment
• A strong analytical and problem solver abilities with excellent verbal and written communication skills