Requirements:
BSc. in Electronic Engineering MSc. an advantage
At least 2 years’ experience as a verification engineer. Completing full development cycle an advantage.
Knowledge in verification methodologies, tools (simulators and relative APIs, coverage tools, accelerators, formal, etc.), and techniques.
Knowledge of Verilog and System Verilog.
Experience in Python / Perl programming.
Good knowledge of Unix environment and script languages.
Methodological approach to building of verification environment and test plan.
Methodological approach to the verification tasks planning and execution.