Minimum Qualifications
Leadership capabilities
5+ years experience as DV engineer.
Eager to succeed.
Accountable & responsible.
Team player.
Great communication skills.
Preferred Qualifications
System Verilog, UVM
Coverage-driven verification.
Power aware simulation.
Gate level simulations.
Co-sim with Matlab/SysC.
ASIC familiar with various design blocks including processors/ micro controllers/ hw accelerators.
System a vast full system understanding.
Leadership capabilities – MUST.
Education Requirements
Required: Bachelor’s, Electrical Engineering or equivalent experience