You will have at least 10+ years of Design Verification experience
We're looking for someone who is well-rounded in all aspects of verification.
You will need to have advanced knowledge of SoC architecture/design & in-depth knowledge of verification flow.
At least 9 years of industry experience in a verification role
Impactful experience developing scalable and portable test-benches
Scripting and programming experience using several of the following: Python, Perl, e, Verilog, SystemVerilog, C, C++, and TCL.
Expected to have a deep understanding and shown experience in advanced verification process, including dynamic, coverage based and formal methods.
Knowledge of System Verilog test-bench language and UVM - Advantage
In this role, you will work closely with the design team to ensure timely delivery of quality designs and be responsible for ensuring bug-free first silicon for part of the SoC / IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures. Develop block, IP and SoC level test-benches. Track and report DV progress using a variety of metrics, including bugs and coverage.
Education & Experience
B.Sc. / M.Sc. Electrical Engineering / Computer Engineering / Computer Science
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