Design Verification Engineer

Minimum Qualifications
• 2-4 years’ experience (at least) in design verification.
• Coding: System Verilog vmm/uvm, Verilog, perl.
• Experience in coverage and in block closure.
Preferred Qualifications
• Hard worker.
• Team member.
• Eager to succeed and learn.
Education Requirements Required: Bachelor's, Electrical Engineering or equivalent experience