We are looking for an experienced Chip design engineer for leading a team of RTL coding of new IPs, SoC integration and implementation, to join our Chip Design team .
• BSc. in Electrical/Communication/Computer engineering from a known university - Must
• 5+ years of experience in ASIC design Frontend or/and Backend - Must
• Familiarity with RTL to GDSII full flow implementation – MUST
• Backend experience- Advantage
• Experience with small geometry process node ( 40nm and below ) –Advantage
• Experience with IR drop/DFT/FPGA – advantage
• Experience in leading a team of chip designers – an advantage
• Team player with good oral and written communication skills.
• Ability to quickly learn new skills, adapt to change and enter new technical fields.