תאריך עדכון | 16/06/2022 |
תיאור המשרה |
Description: In your role you will be implementing block/sub-system level logic design RTL using System Verilog. You will be involved in deep understanding of the design at multiple levels: the micro-architecture, features and specification. You will be working with pre-silicon validation engineers to validate the design and fix design bugs and physical implementation team. You must be a team player, willing to go the extra mile to achieve success.
Skills required: · BSc or Msc in Electrical and Electronic engineering – MUST · 4+ years of experience in VLSI & RTL coding – Must · Scripting knowledge – Must (Python, Perl, TCL …) · Team player with excellent oral and written communication skills · Ability to quickly learn new skills, adapt to change and enter new technical fields · Knowledge in Cryptography / Security – an advantage · Familiarity with the following tools : Design Compiler, ICC, Primetime, Formality, Tetramax– an advantage · Familiarity with RTL to GDS full flow implementation – an advantage
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