* B.Sc. or MSc in Electrical Engineering
* 3 years in Back-end design in advanced technology nodes with either Synopsys or Cadence tools
* Deep knowledge in Back-end flows RTL-GDSII, Physical Synthesis, Floorplan, P&R, CTS, STA and Power Analysis
* Scripting & Programming skills in Perl and TCL.
* RTL/DFT Design background – advantage
* Advanced process experience (16nm/12nm) – advantage
* Good inter personal relationship and should be able to work in a team and be a good team player