Back-end Physical Design Engineer

Description
– 1+ years experience in physical design of large scale SoC
– Extensive experience with one of the place & route tools available today (Synopsys / Cadence). Familiar with hierarchical design approach, top-down design, timing and physical convergence
– In-depth understanding of static-timing analysis, extensive know-how in clock/power distribution and analysis, RC extraction and correlation.
– Experience with SoC practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.
– Scripting and programming experience using several of the following: Perl, TCL and Make
– Knowledge in Verilog – advantage
Position is available for both Herzliya/Haifa sites.