ASIC Expert

Tasks:
Help with chip architecture definition.
Convert FPGA design into an ASIC.
Work with the algorithm team to implement MATLAB based algorithms into an FPGA.
Implement new design features in FPGA.

B.Sc. in electrical engineering from a known university.
7 -10 years' experience with Verilog in FPGA and ASIC design.
Experience with designing for ASIC
Knowledge in RTL to GDSII flow.
Experience with Xilinx's FPGAs and tools - Advantage.
Experience with LVDS communication channels - Advantage.