Requirements:
•Graduate of B.Sc. or M.Sc. in electrical/communication engineering or equivalent, average grade >82
•Good System understanding
•Great communication skills
•Great team player
Advantages:
•Hands-on experience in one or more of the following ASIC area:
oPHY / signal processing
oMAC and Network
oSOC and MCU, Power Management / Low power architecture
oProgramming language Verilog/System Verilog
•RTL Synthesis experience
•STA experience
•Programming/scripting languages: python, Perl, C, Matlab etc.
•Formal tools (e.g LEC, CDC)
•Relevant standards – 802.11 Mac and/or PHY, TCP/IP, TLS/SSL
•Security protocols
