Application Engineer- Verification

• This position requires a solid understanding of simulation-based verification flows such as RTL
and GLS as well strong proficiency in Verilog/ SystemVerilog/ VHDL/ Specman-e.
• You will also be required to possess good understanding of common verification flows and
methodologies such as the UVM/OVM, Coverage-Driven Verification, Assertion-based
Verification, Low-Power Verification and so forth.
• Familiarity with the full SoC design flow is an advantage, as well as some knowledge of common
protocols such as AXI, AHB, USB, PCIe, etc.
• CAD experience is a plus.
• This job requires a minimum of 5-10 years verification hands-on experience.
• Strong verbal and written communication skills in English. Good problem-solving skills.