Analog Layout Engineer

What will you be doing?
Execute tasks covering all IC’s layout flow.
Examine new technologies and PDK’s.
Conceptual floor-plans.
High precision and sensitive analog block level.
Full chip and complicated top level layouts including running full Takeout flow.
Interface with professional engineers to deliver pioneering analog circuits.
Requirements:
At least 3 years of experience in analog VLSI layout.
Covering all analog layout aspects including sensitive analog blocks layout techniques: from block level to full chip top level.
Using Calibre and Cadence flow and layout extraction flow.
Multi-tasking ability and covering several projects simultaneously.
Layout experience in High voltage PDK’s such as BCD process.
It would be great advantage if you are:
Familiar with IOs and ESD layouts.
Familiar with layout verification tools (Calibre, PVS).
Experienced in scripting languages (Perl, Python) and CAD background.
Experience with Post silicon measurements at lab.